1. Field of the Invention.
The present invention relates to analog-to-digital (A/D) converters and, more particularly, to an A/D converter that corrects for both component mismatch and nonlinearity errors.
2. Discussion of the Related Art.
Analog-to-digital (A/D) converters rely on the values of components, typically resistors or capacitors, to form ratios that digitally represent the ratio of an input signal to a reference signal. As a result, the primary limitation on the accuracy that can be achieved with an A/D converter is the variation in the values of the components. This variation, known as component mismatch, causes these ratios to deviate from their nominal values which, in turn, produces errors in the digital representation of the input signal.
A switched-capacitor A/D converter architecture, for example, is typically limited in resolution to about 10-12 bits by mismatches between the capacitor values. Since applications are creating a demand for A/D converters with much greater accuracy, a number of methods have been devised for improving component matching or correcting the errors introduced by mismatches.
For example, components can be laser trimmed to improve the matching. This extra step, however, adds considerable cost to the fabrication process. Another approach, described in K. S. Tan, et al., "Error Correction Techniques for High-Performance Differential A/D Converters," IEEE J. Solid State Circuits, Vol. 25, No. 6, pp. 1318-1326, December 1990, is to store a digital correction signal, convert it to the analog domain, and then subtract the analog correction signal from the analog input signal. The disadvantage of this technique, however, is that it requires one or more extra digital-to-analog converters which consume additional power and die area.
Mismatch errors cause abrupt discontinuities in the input/output characteristic of an A/D converter, whereas nonlinearity errors, which are caused by the nonlinearity of the devices and circuits that are in the analog signal path, can be modeled as a continuous polynomial in the input signal with the terms of the polynomial decreasing in magnitude as the order of the terms increases. The first two terms (the constant and linear terms) can be interpreted as errors in the offset and gain of the device and are thus not important sources of error since they do not produce any distortion. Second-order and higher even-order nonlinearities can be approximately canceled by using a fully differential circuit architecture. Thus, the most important nonlinearity error will usually come from the third-order term.
In a typical switched-capacitor A/D converter, the third-order term limits the accuracy of the converter to about 13-14 bits. One technique for dealing with this error source utilizes an analog circuit to reproduce the third-order distortion to cancel it out. See R. Hester, at al., "Analog to Digital Converter with Non-linear Capacitor Compensation", 1989 Symposium on VLSI Circuits Dig. of Tech. Papers, pp. 57-58 and U.S. Pat. No. 4,975,700 to Tan, et al. The principal limitation to the Hester et al. approach is that this approach requires a significant amount of additional analog circuitry which, in turn, increases the cost and complexity of the converter. In addition, circuitry for removing the higher-order nonlinearities becomes increasingly difficult to design.
Another technique, described in U.S. Pat. No. 5,047,772 to Ribner, utilizes a digital memory to introduce an additive correction which is chosen based on a roughly quantized representation of the input signal. Several other independent digital memories are used to introduce corrections for component mismatches. This technique is able to correct for both component mismatch and circuit nonlinearity errors. The primary drawback of this technique is that it requires a much larger number of correction coefficients to be stored in a digital memory, which increases the area consumed by the error correction circuitry, and thus increases the cost and complexity of the analog-to-digital converter.
Another approach that has been used to increase the accuracy of A/D converters is described in U.S. Pat. No. 4,894,656 to Hwang et al. In this technique, a series of coefficients are stored representing the error at several different output codes of the A/D converter, and linear interpolation is used to determine an additive correction to the output code. While this technique is efficient in its utilization of memory, it is not able to correct for component mismatch errors since it is not possible to represent a discontinuous function using a linear interpolation technique.